Product Overview

VMIVME-2540 is a 24 channel intelligent counter/controller that serves as a slave I/O module for VMEbus systems, providing high-precision digital measurement and function generation capabilities. It features a simple and consistent memory mapped user interface. It consists of three parts: a VMEbus slave DTB interface, a CPU with firmware and supporting logic, and a circuit for implementing measurement and control functions. It is equipped with a 15 MHz 68HC000 CPU, supports A32/A24/D32/D16/D8 (EO) VMEbus slave interfaces and a 64 Kbyte VMEbus memory window. The data exchange interface complies with ANSI/IEEE standard 754-1985 (32-bit floating-point operation).

Core functions and parameters

Measurement function

Event Count: Up to 4 billion events, with an input frequency range of up to 2.5 MHz. The counting range can reach 232 in long mode and 216 in word mode.

Frequency measurement: ranging from -1.16 × 10-3 Hz to 2.5 MHz; The maximum accuracy of a 16 bit counter is 0.015% between 0.007 and 76 Hz, and the error is 100 × (frequency/5 MHz) between 76 Hz and 2.5 MHz; The 16 bit enhanced resolution counter (requires two 16 bit counters) has a range of 0.001 Hz to 1.25 MHz.

Cycle/pulse width measurement: Supports 16 bit and 32-bit, discrete or continuous modes, with low data transmission latency. The range of a 16 bit counter is 131.07 s to 400 ns, and the range of a 16 bit enhanced resolution counter (requiring two 16 bit counters) is 858.9 s to 800 ns. In 32-bit integer operations, two 16 bit counters are required for pulse width measurement, and three 16 bit counters are required for cycle measurement.

Orthogonal position measurement: sine/cosine input range from DC to 1 MHz, 32-bit counter, supports limit/modulus check, accuracy is ± 1/4 wave (5 MHz sampling rate), each encoder requires two channels.

Generate function

Square wave/pulse sequence generation: frequency range from 0.0076 Hz to 2.5 MHz.

Timer/Periodic VMEbus Interrupter: Frequency range from 0.0076 to 1000 Hz.

Pulse sequence mode: can generate a sequence of N pulses, with programmable duty cycle.

Orthogonal position control output: ± 1/4 wave control resolution, up to 1.25 MHz step speed and ± 32767 steps/command.

Other functions

Event triggered timer delay: Generate VMEbus interrupt at most 131.1 seconds after input at the event edge, which can be triggered again.

24 control/measurement interfaces: including 24 clocks, 24 gates, and 24 outputs.

Supports RS-422 differential interface and single ended TTL input.

Options for configuring 4, 8, 16, and 24 interfaces.

System and Physical Specifications

System time base: 5 MHz, accuracy/stability of ± 0.005%.

Power requirements:+5 V ± 5/-2.5%, typical 4.25 A, maximum 5 A.

Temperature range: Operating temperature from 0 to 65 ° C, non operating temperature from -40 to 85 ° C, humidity from 5 to 95% RH without condensation.

VMEbus compatibility: Complies with ANSI/IEEE 1014-1987, IEC 821 and 297, supports A32/D32 DTB slaves, base address can be selected on a 64 Kbyte boundary, supports monitoring/non privileged address modification codes, dual interrupt module can assert any one of IRQ1 to IRQ7, board size 160 × 233.4 mm.

Input/output buffer specifications

Input buffer

Common mode voltage limit: ± 25 V.

Differential mode voltage limit: ± 5 V (due to 1/4 W, 120 Ω terminal resistance).

Differential mode V IH/V IL: Compliant with RS-422 standard, V IH refers to the main (positive) input voltage being 100 mV higher than the differential (negative) input voltage within the ± 25 V common mode voltage range; V IL refers to the main (positive) input voltage being 100 mV lower than the differential (negative) input voltage within the ± 25 V common mode voltage range.

Single pole (single ended) mode V IH/V IL: V IH=V TTL+100mV, V IL=V TTL − 100mV.

Input lag: 50 mV.

Suggested input rise time: minimum 5 ns, typical propagation delay 25 ns, maximum 1 ms.

Output buffer

AM26LS31 is used.

Short circuit current: Typical I SC=-60mA.

Differential output voltage: minimum ∣ V t ∣=2V.

Interface and Connection

Discrete wire connectors and terminal blocks: It is recommended to use connector components from Harting Elektronik, Inc., such as 96 pin discrete wire connectors (model 0903-096-3214).

RS-422 differential signal: Twisted pair insulated wire (24 AWG solid or multi stranded copper conductor) should be used,

R<30Ω/1000

ft）， The maximum cable length is 4000 feet, and it is necessary to ensure that each signal group is properly grounded.

TTL signal: 96 conductor flat ribbon cable (30 AWG insulated copper multi strand conductor) can be used, corresponding to ERNI 913.031 or similar 96 pin DIN female connector. It is recommended that the total cable length not exceed 50 feet.

If the front panel I/O signal needs to be led out to the terminal block, it is recommended to use VMIAC-BT04 dual 96 pin transition panel and connect it through a 96 conductor ribbon cable (recommended to be 3 feet long).

Application field

Including rotary axis instruments (angular position, velocity, acceleration), automotive industry testing (brakes, transmissions, tachometers), robotics, telescopes/observatories, medical/laboratory instruments, linear position measurement (distance, velocity, acceleration), elevators, bridge cranes, X-Y workbenches, machine tools, automatic storage and retrieval, etc.

Product Overview

Basic introduction: VMIVME-2511 is a programmable I/O board compatible with VMEbus. It uses two Motorola MC68230 parallel interface/timer chips and one Motorola MC68153 bus interrupt module, with multiple functions and features.

Key Features

48 bit I/O (including bit I/O, unidirectional 8-bit and 16 bit, bidirectional 8-bit and 16 bit).

Interrupt generation logic, supporting four interrupt sources, each MC68230 has one timer interrupt and one port interrupt.

Optional high current driver with a current filling capacity of up to 64mA.

Two 24 bit programmable timers, supporting software programmable timer mode.

Optional handshake timer that can be connected to various low-speed, medium speed, or high-speed peripherals or other computer systems.

Equipped with Centronics parallel interface.

Physical description and specifications

Physical description: Composed of VMEbus compatible logic, interrupt control logic, and I/O control logic related to parallel interface/timer modules. VMEbus compatible logic includes address decoding logic and data transmission control logic, supporting VMEbus read and write data transmission; The interrupt control logic utilizes Motorola MC68153 BIM to allow port and timer interrupts from each parallel interface/timer; The parallel I/O port is programmable and supports multiple modes. The high current driver option can provide up to 64mA of surge current capability, but does not support bidirectional mode. If the bit I/O mode is selected, all A port data bits must be programmed in the same direction.

Features

Compatibility: Complies with VMEbus specifications and adopts dual height external dimensions.

I/O connector type: 64 pin connector (DIN 41612).

I/O organization: Utilizing two Motorola MC68230 parallel interfaces/timers, providing multiple programmable I/O functions, buffered I/O options have driver capability limitations and do not support bidirectional mode.

Addressing scheme: An 8-bit DIP switch provides board address, and the factory default configuration is to respond to short monitoring I/O access. Users can change it to short non privileged I/O access through jumper wires.

Data polarity: can be ordered as high or low validity.

Electrical specifications: Provide parameters such as output high voltage, output low voltage, input high voltage, input low voltage, output high current, and output low current for both without and with I/O buffer.

Physical specifications

Environment: Operating temperature from 0 to 55 ° C, storage temperature from -20 to 85 ° C; relative humidity from 20% to 80%, no condensation; The cooling method is convective cooling.

Power requirement:+5V, maximum 2.5A.

Ordering information: The ordering model of VMIVME-2511 includes multiple options, including key, output options, input options, data transmission, I/O options, output resistance options, input voltage, output type, input type, etc. The input and output polarity options must be the same, and compatible connectors, strain eliminators, and PC board connectors are also provided.

Operating principle

Block diagram: VMIVME-2511 consists of 10 main subsystems, each with a detailed block diagram, including address decoding subsystem, parallel interface/timer and I/O port control logic, VMEbus interrupt subsystem, etc.

Operation Overview: Two MC68230 modules are respectively associated with P3 and P4 connectors. I/O data transmission is achieved by selecting registers on the required P/I/T modules, interrupt processing is implemented by programming the selected P/I/T modules, and the corresponding channels in 68153 BIM are enabled to enable specific interrupt sources to be responded to by the system processor. Some jumper selections vary depending on the port channel function of the P/I/T module.

I/O data transfer description: I/O transfer is performed through P3 and P4 connectors, with the help of port registers on the required P/I/T module. When equipped with optional buffers, I/O operations are a subset of the P/I/T module functionality, which limits programmability but enhances driving capability.

Interrupt capability: capable of handling four interrupt requests, with each P/I/T module supporting two requests (port interrupt request and timer interrupt request)

Main features of the product

The direction of each 8-bit port can be individually programmed.

Capable of injecting 64mA current.

The control register and data register use independent board address decoding.

Built in testing (BIT) logic for fault detection and isolation.

Equipped with fault LED indicator light.

Compatible with VMIC’s intelligent I/O controller product line.

Adopting high reliability DIN type I/O connectors.

Supports 8-bit, 16 bit, and 32-bit data transmission.

Optional open electrode output.

Functional characteristics

Compatibility: Complies with VMEbus specifications and adopts dual height external dimensions.

I/O connector type: Dual 64 pin DIN connector.

I/O organization: 8 I/O ports, each 8 bits wide, addressable to any address within a short monitoring or short non privileged I/O mapping.

Addressing scheme: 8 ports can be individually addressed on 8-bit or 16 bit boundaries, and address DIP switches provide unlimited short data I/O address mapping options.

Built in testing: Output data can be read back in real-time or in offline mode. Offline mode is enabled by writing to the control and status register (CSR) to set the test mode bit. When the test mode is enabled, all outputs are in three states, providing two test mode bits. If necessary, each connector’s I/O (32-bit) can be independently tested.

Fault LED: It lights up during power startup and system reset, and can be turned off after successful diagnosis under program control.

I/O circuit: The transceiver supports high current input (64mA) output, and the logic level TTL I/O option uses the SN74AS645 octal bus transceiver. The open collector electrode option uses the SN74AS641 transceiver. If the open collector electrode option is ordered, all 64 bits are only output.

Product model: There are multiple models of this product, with 2510 being the original design (one test mode bit); 2510A has two test mode bits (one for each connector); 2510B is recommended for new designs (two test mode bits).

Ordering Options

A (input/output type and data polarity): 1 is TTL logic level input and output, positive logic; 2 is TTL logic level input and output, negative logic; 3 is an open electrode output (no input), positive logic; 4 is an open electrode output (no input) with negative logic.

B (output resistance): 0 is an uninstalled resistor; 1 is 2.2k Ω (open collector electrode input/output must be selected).

C. D and E: 0 are unused.

Connector data

Compatible cable connector: Panduit No. 120-964-435E.

Strain eliminator: Panduit No. 100-000-032.

PC board header connector: Panduit No. 120-964-033A.

Physical/Environmental Characteristics

Temperature range: Operating temperature from 0 to 55 ° C, storage temperature from -20 to 85 ° C.

Relative humidity range: 20% to 80%, no condensation.

Cooling method: convective cooling.

Power requirement:+5V, maximum 3.786A.

Positive/negative logic ordering information

TTL I/O: The positive logic input option presents a high-level input voltage on each data line corresponding to logic 1 on VMEbus; The positive logic output option presents logic 1 to the output data register (ODR), presenting a high-level output voltage on each data line. The negative logic input option presents a high-level input voltage on each data line corresponding to logic 0 on VMEbus; The negative logic output option presents a logic 0 to the output data register and a high-level output voltage on each data line.

Open collector electrode output option: The positive logic output option presents logic 1 to the ODR (the corresponding bit on VMEbus is logic 1), causing the output open collector electrode transistor to conduct and provide grounding for the load; The negative logic output option presents logic 0 to the ODR (with the corresponding bit on VMEbus being logic 1), causing the open collector electrode output transistor to turn off.

IIOC compatibility

This product is compatible with VMIC’s Intelligent I/O Controller (IIOC) series and is suitable for fields such as data acquisition, process control, factory automation, as well as simulation and training markets. The IIOC software supports the I/O of this product, allowing users to load the direction of I/O on each connector offline. Therefore, IIOC does not support separate port control, and its support is limited to VMIVME-2510A or -2510B models. IIOC is a multiprocessor controller that includes a CPU, global memory, various optional host interfaces, and firmware, providing a complete I/O solution.

Product Overview

Basic function: VMIVME-2128 can provide 128 channels of high voltage and/or high current surge current output. Its open collector electrode output driver supports output voltages from 5 to 48VDC and has built-in test (BIT) logic, allowing users to verify the operation of each channel under software control.

Key Features

128 channel high-voltage digital output (5 to 48VDC), supporting 8-bit, 16 bit, or 32-bit VME data transmission.

High current open collector electrode driver (600mA current) with built-in suppression diode, output can be connected in parallel for higher driving capability, optional open collector electrode pull-up resistor.

The output has fault protection function (when the current exceeds 1.0A, the output is turned off), built-in testing logic, and a software controlled fault LED on the front panel (for built-in testing).

Users can configure address jumpers to allow for continuous addressing of multiple boards when used in a VME system.

Application scenarios: Suitable for various applications such as relay drive, lamp drive, solenoid drive, hammer drive, stepper motor drive, LED drive, high current and high voltage drive, fiber optic LED drive, etc.

Security Summary

To minimize the risk of electric shock, the chassis and system cabinets must be connected to electrical grounding, using three core AC power cords, and correctly connected to grounded sockets.

Do not operate the system in an explosive atmosphere to avoid potential safety hazards.

Operators are not allowed to remove the product casing. Component replacement and internal adjustment must be carried out by qualified maintenance personnel. When replacing components, do not connect the power cord. Even if the power cord is removed, there may still be dangerous voltage in some cases. Before contacting the circuit, the power supply must be disconnected and discharged.

Do not perform internal repairs or adjustments alone, personnel who can provide first aid and resuscitation must be present.

Do not replace components or modify the system to avoid introducing additional hazards. Product repairs should be returned to the GE Fanuc embedded system to ensure that safety functions are maintained.

Dangerous program warning: There will be a warning in the manual before potential dangerous programs, and the instructions in the warning must be followed.

Safety symbols

STOP: Inform the operator not to perform a certain operation, as it may result in personal injury or partial or complete damage to the system.

Warning: Indicates the presence of danger and reminds attention to a certain procedure, operation, or condition. Improper execution or compliance may result in personal injury or death.

CAUTION: Indicates the presence of danger and reminds attention to a certain operating procedure, operation, or condition. Improper execution or compliance may result in partial or complete damage to the system.

NOTE: Remind attention to an important program, operation, or condition.

Operating principle

Functional modules: The design of the VMIVME-2128 board mainly consists of four parts: VME basic logic, device addressing, output drivers, and built-in test logic. It supports eight 16 bit bidirectional registers, one control and status register (CSR), high-performance output drivers, typical VME basic logic, and device address jumper groups, which allow users to select the base address.

Device Addressing: Supports data transfer in short or standard I/O memory space, with monitoring and/or non privileged data access capabilities. The I/O access type is selected through jumper wires, and the factory defaults to responding to short monitoring I/O access.

VME basic logic: composed of drivers, receivers, and control logic, the DTACK generator is designed to provide high data transmission rates.

Data transmission: The data transmission transceiver supports read and write operations on 8-bit, 16 bit, and 32-bit boundaries.

Register control logic: Supports read and write operations on eight 16 bit bidirectional dual port latches, as well as read operations on CSR registers that control test modes and front panel LEDs. The 128 bit high voltage output can be addressed as four 32-bit long words, eight 16 bit words, or sixteen 8-bit bytes.

Built in testing (BIT): By enabling the test mode bit in CSR, test data can be written to any output data register (ODR) in test mode and read back during read operations. At this time, all drives are turned off (tri state), and ODR can be read independently of the test mode bit at any time. This function provides real-time loopback testing (when the output driver is connected) and offline diagnostic testing (when the output driver is disconnected from the field device) capabilities. The front panel has a fault LED for quick fault isolation to the board level. The fault LED lights up when powered on or the system is reset, and the user can turn it off after successful diagnosis.

Output driver: Equipped with thermal and surge current shutdown protection, surge current protection allows up to 990mA of surge current before the driver shuts down. If the surge current of each channel in the external circuit exceeds the 990mA limit, preheating resistors should be used. SIP resistor sockets are provided on the board for these preheating resistors, which must be of bus type, with pin 1 as the common terminal and pin 1 of the socket grounded. The power rating of the SIP resistor should be sufficient to handle the required power consumption. The output driver user load return current must provide the lowest possible resistance return path to the user voltage source, and must not be returned through VME backplane digital ground. It must be returned to the user power supply through the B-row pins of the front panel connectors P3 and P4, or through pins A1 to A26 of the P2 connector if the P2 user ground option is ordered. If the user’s grounding quality is poor, causing the user’s load to return current to the digital grounding of the backplane, fuse F1 will melt and make the board unable to work. A blown fuse usually indicates poor grounding quality for the user, and this fuse circuit is necessary for the digital input grounding return of the control signal to the output driver.

P2 user grounding option: The user grounding is connected to all B-row pins of the front panel connectors P3 and P4. If the P2 user grounding option is ordered, these grounds are also routed to pins A1 to A26 of the backplane P2 connector through the installation of short-circuit bars SB1 to SB4 (RP33 to 36). The external power supply grounding (user grounding) can now be accessed from the P2 backplane connector of the VME chassis. All 26 wires are required to provide a low resistance user load current return path. For a typical 300mA/channel load, the current of each wire can reach up to 1.48A. Each unused wire means that its current must be shared by the remaining wires, so 28 AWG or larger wires should be used.

Configuration and Installation

Unpacking procedure: Some components on GE Fanuc embedded system products may be sensitive to electrostatic discharge. When placing the board on a workbench for configuration and other operations, it is recommended to insert conductive material underneath the board to provide conductive diversion. Unused boards should be stored in their original packaging. After receiving the product, all precautions in the transport container should be followed, all items should be carefully unpacked, and a thorough inspection should be conducted for any transport damage. All claims arising from transport damage should be made to the carrier and a complete report should be sent to the GE Fanuc embedded system, requesting advice on the handling of damaged items.

Jumper and switch positions: Introduces the physical positions on the jumper, and the address modifier can change the configuration by installing the jumper at the appropriate position on connector H1, supporting multiple I/O access types. The address selection jumper is used to specify the starting board address for data transmission. The installed jumper is equal to zero, and the omitted jumper is equal to one. The factory default configuration is to respond to 0000 HEX in the short monitoring space.

I/O cable and front panel connector configuration: The output connectors (P3 and P4) on VMIVME-2128 are 96 pin DIN standard and can be used with various cables and matching connectors. Users can refer to the relevant application guide for more information. Detailed explanation of the use of user I/O pins and external voltage input for connector P2, as well as the pin configuration of output connectors for P3 and P4. The VMIVME-2128 board is designed with a high-quality ground plane, which is connected to the VME ground through fuse F1 and to the B-row pins on connectors P3 and P4 to enhance noise resistance and improve operational reliability. Users are also reminded that the grounding conductor should be connected to the power supply (GND return) associated with these signal loads, and the grounding connection should prevent excessive current (DC or noise) from flowing through the VME backplane. External user voltage should not be applied to VMIVME-2128 without connecting the VME backplane+5VDC. If these voltages cannot be applied and removed together, the preferred order is: user voltage is connected last and disconnected first.

Optional user grounding: If the user grounding option is ordered, the output return is routed to pins A1 to A26 of P2 through the installation of short-circuit bars SB1 to SB4, allowing access to the external power supply grounding from the P2 backplane of the VME chassis. It is important to maintain the grounding path resistance lower than the VME grounding path resistance and use as many wires as possible to lead out these grounding points. The current in the wires may be large, so 28 AWG or larger wires should be used, while being careful not to exceed the maximum current rating of the connector pins.

Preheating resistor: When the incandescent lamp is initially turned on, the cold filament resistor is the smallest, usually allowing 10 to 12 times the surge current. A surge current of 1A or greater will force the output driver to enter the return current limit. To avoid this problem, preheating or current limiting resistors should be used in the lamp circuit. The preheating resistor should consume about 10% of the rated (hot) current of the bulb. A ten pin SIP socket is provided on the board for preheating resistors, which must be bus type, with pin 1 as the common terminal and pin 1 of the socket grounded. The power rating of the preheating resistor should be sufficient to handle the required power consumption.

Programming

Register Mapping: VMIVME-2128 includes a 16 bit board ID register, a 16 bit CSR, and eight 16 bit ODRs, providing register address mapping. ODRs allow control of 128 high-voltage digital output channels, which can be addressed as four 32-bit long words, eight 16 bit words, or sixteen 8-bit bytes. ODRs can be read under program control for data verification or diagnostic testing. CSR and board ID can be addressed as 16 bit words or two 8-bit bytes, and ID and CSR bit mappings as well as ODR bit mappings are provided. The board uses a 32 byte address space.

Detailed programming: In output data transmission, the data register address mapping displays the correspondence between ODR (DR0 to DR7) and output data channels 127 to 0. The built-in testing function provides real-time loopback data verification and offline diagnostic execution capability. The offline built-in testing function is activated by setting the test mode (TM) bit in CSR to logic “zero”. When the TM bit is set, all output drivers are in three states, and test data can be written into the selected data register and read back during read transmission without affecting the user device. When the test mode is turned off, the data can also be read back, allowing online testing of the board. The test mode bit and fault LED control bit are initialized to active state when powered on or system reset, so the fault LED lights up and the output driver is disabled. A simplified programming flowchart is also provided.

Maintenance

When a product malfunctions, it is necessary to first check the software, system configuration, electrical connections, jumper or configuration options, whether the board is fully inserted into its correct connector position, whether the connector pins are clean and free of contaminants, whether there are components or adjacent boards disturbed when inserting or removing the board from the chassis, and the quality of cables and I/O connections.

If you need to return the item, you need to contact GE Fanuc Embedded System to obtain a Return Merchandise Authorization (RMA) number, which can be obtained via email. Customer service can also be contacted by phone or email.

User level maintenance is not recommended, and the drawings and charts in the manual are for reference only.

Product Overview

Basic information: VMIMPC-5790 is a device based on LSI Symbios ®  The PMC dual channel Ultra160 SCSI host adapter of SYM53C1010 highly integrated PCI dual channel Ultra160 SCSI controller is suitable for embedded applications that require high throughput. It can maximize throughput while reducing transmission latency and host processor overhead. The host BIOS configures it as two independent Ultra160 SCSI channels.

Hardware features

64 bit, 33/66 MHz PCI interface, no external memory required.

Dual transition clock, with a throughput of up to 160 Mbyte/s per channel, supporting 64 bit addressing through dual address cycles (DACs).

Compliant with PCI 2.2, PCI Power Management 1.1, and PC99 standards, it has functions such as cyclic redundancy check (CRC), domain validation, and asynchronous information protection (AIP).

High performance PCI multifunctional device, presenting only one electrical load to the PCI bus, with two independent wide Ultra160 SCSI channels, equipped with SCSI Interrupt Steering Logic (SISL) backup interrupt routing, supporting Nextreme ™  RAID。

Operating System Support: Supports Windows NT and 95/98, Novell NetWare, Linux, Solaris, UnixWare, OS/2, and other operating systems.

Target applications: Storage Area Networks (SANs), server cluster environments, embedded RAID, low-cost PCI host adapters, host motherboards, etc.

Function Description

Core controller: using Symbios ®  The SYM53C1010 controller is fully compatible with the Ultra160 SCSI standard and supports multiple standards such as Fast SCSI, Ultra SCSI, Ultra2 SCSI, and Ultra160 SCSI. The dual transition clock enables a throughput of up to 160 Mbyte/s for each channel and a total throughput of 320 MBps, without the need to increase the interface clock frequency.

Data protection: Using the same CRC algorithm as FDDI, Ethernet, and Fiber Channel, it can detect various errors; AIP protects all non data stages and enhances the CRC function of Ultra160; SureLINK ™  Domain validation technology can detect SCSI bus configuration and automatically test and adjust transmission rates. The controller also has Margining (Level 3) domain validation function.

PCI Interface: Complies with PCI Local Bus Specification Revision 2.2, implements 64 bit/66 MHz PCI bus, backward compatible with 32-bit/33 MHz bus, is a true PCI multifunctional device, uses a REQ/- GNT/pair to arbitrate PCI bus master, generates separate interrupt signals for SCSI functions A and B, supports multiple power states and extended access cycles.

SCSI memory: Supports up to 1 Mbyte of external expansion ROM through parallel interfaces, supports local programming FLASH memory, and the serial 2-wire interface on each SCSI channel can be connected to external serial EEPROM for storing subsystem vendor IDs and subsystem IDs.

SCSI Processor: Provides two independent Ultra160 SCSI controllers on a single chip, integrated with LVDlink ™  Transceiver, supports LVD and single ended signals without the need for an external transceiver. The on-chip SCSI clock quadrupler enables the chip to achieve Ultra160 SCSI transfer rate at an input frequency of 40 MHz, with 8 Kbytes of internal RAM per channel for SCRIPTS ™  Instruction storage, 944 byte DMA FIFO can efficiently transmit data in bursts.

SCSI terminal: All SCSI buses require terminal networks at both ends. The host adapter uses UCC5630A terminal IC to automatically detect the SCSI bus and switch terminal modes. The device type is determined based on the type of device connected to the bus, and the device type is identified through the DIFSENS signal line. Header E1 pins 3 and 4 enable automatic terminal function.

Media connection: Supports dual 68 pin VHDCI external connectors.

Software Drivers: To optimize the performance of PCI based adapter cards, provide software drivers compatible with the Windows NT operating system, which can be obtained through the VMIC website or by contacting customer service for drivers not available on the website.

Reference List

For detailed instructions on the PCI local bus, please refer to the PCI local bus specification and obtain it from the PCI Special Interest Group.

For detailed instructions on SCSI, please refer to the fourth edition of Basics of SCSI and obtain it from Ancot Corporation.

For a detailed explanation of the SYM5301010 dual channel Ultra3 SCSI controller, please refer to the relevant documentation and obtain it from LSI Logic Corp.

For detailed instructions on the UNITRODE UCC5630A multi-mode SCSI 9-wire terminator, please refer to the relevant data manual obtained from UNITRODE Corporation.

The physical description and specifications can be found in the product specification document, which can be obtained from VMIC.

Security Summary

To minimize the risk of electric shock, the chassis and system cabinets must be connected to electrical grounding, using three core AC power cords, and correctly connected to grounding sockets.

Do not operate the system in an explosive atmosphere to avoid creating a safety hazard.

Operators are not allowed to remove the product casing. Component replacement and internal adjustment must be carried out by qualified maintenance personnel. When replacing components, do not connect the power cord. Even if the power cord is removed, there may still be dangerous voltage in some situations. Before contacting the circuit, the power supply must be disconnected and discharged.

Do not perform internal repairs or adjustments alone, personnel who can provide first aid and resuscitation must be present.

Do not replace components or modify the system to avoid introducing additional hazards. Product repairs should be returned to VMIC to ensure that safety functions are maintained.

Dangerous program warning: There will be a warning in the manual before potential dangerous programs, and the instructions in the warning must be followed.

Safety symbols

Multiple safety symbols are used in the manual, representing dangerous voltage, protective conductor terminals, low-noise or noiseless clean grounding terminals, frame or chassis terminals, AC power supply, DC power supply, AC/DC power supply, prohibited operation (which may cause personal injury or system damage), warning (which may cause personal injury or system damage), caution (which may cause system damage), attention (emphasizing important information), etc.

Operating principle

PCI Addressing: There are three types of PCI defined address spaces: configuration space, memory space, and I/O. The configuration space is a continuous set of addresses dedicated to each “slot” or “stub” on the bus. Ultra160 SCSI contains two sets of configuration registers, which BIOS uses to initialize devices and determine whether to access the configuration register space through C_BE [7:0]/decoding. The IDSEL bus signal is “chip selection”, which allocates base addresses for memory access and I/O access during initialization, and accesses by comparing the base address with values on the address/data bus.

Supported PCI bus commands: Bus commands indicate the transaction type requested by the target host device, encoded through C_BE [7:0]/line in the address phase, and support multiple command types such as I/O read cycle, I/O write cycle, memory read, memory write, etc.

PCI bus configuration register: The configuration register is only accessed by the system BIOS during the PCI configuration cycle and cannot be accessed by users. It includes various registers such as device ID, vendor ID, status/command register, class code/revision ID register, etc. Each register has its specific bit definition and function.

SCSI interface registers: The control registers of the SCSI core can be directly accessed from the PCI bus through memory or I/O mapping. SCSI functions A and B contain the same register set, and the address mapping table lists the addresses and names of each register. The phase mismatch register contains the byte count and addressing information required to update the direct, indirect, or table. The host CPU can only access some registers when executing SCRIPTS in SYM53C1010.

Configuration and Installation

Unpacking procedure: Product components are sensitive to static electricity and should be placed on conductive materials during handling. When not in use, they should be stored in their original packaging. Upon receipt of the product, it should be checked for any transportation damage. If so, a claim should be made to the carrier and VMIC notified.

Physical installation: Do not power on when installing or removing the board. The appearance and installation program of the PMC slot in the host system differ greatly. It is recommended to first check the host system installation program. The installation steps include removing the motherboard, installing the board to the PMC connector and fixing it, reinstalling the motherboard and powering it on. The board design complies with relevant PCI signal specifications.

Cable configuration: The SCSI connection uses a dual channel 68 pin VHDCI external connector. The front panel SCSI connector consists of two 68 position VHDCI right angled stacked sockets, representing channels A and B respectively, which can connect multiple SCSI devices. Terminal handling should be noted. When Ultra160 SCSI uses low voltage differential (LVD) signals, the cable length can reach 12 meters, and a single channel can connect up to 16 devices.

Maintenance

When a product malfunctions, it is necessary to first check the software, system configuration, electrical connections, jumper or configuration options, card insertion status, connector pin cleanliness, adjacent card components for interference, cable and I/O connection quality, etc.

If you need to return the item, you need to contact VMIC to obtain a Return Merchandise Authorization (RMA) number. Customer service can be contacted by phone or email.

User level maintenance is not recommended, and the drawings and tables in the manual are for reference only.

SCSI BIOS and Configuration Utility

SCSI BIOS: It is bootable ROM code that manages SCSI hardware resources, integrates with standard system BIOS, extends the standard disk service program provided through INT13h, initializes at boot time, determines the installed hard disks in the system, and maps SCSI drives.

Start SCSI BIOS Configuration Utility: During the boot sequence, this utility can be used to change the default configuration of the SCSI host adapter. Press “Ctrl-C” to start when a specific message is displayed on the screen. If all controllers are disabled, press a specific key combination to reactivate and configure them during restart.

Using the configuration utility: The screen is divided into a title area, menu area, main area, and footer area, each with its own functions. Users can operate them through specific keys, such as F1 for help, arrow keys for selecting items, etc.

Main menu: After calling the utility, it displays a list of up to 256 LSI Logic PCI to SCSI host adapters and their information in the system. You can select the adapter to view and modify its properties, or choose to start the adapter list and global properties options.

Startup adapter list: Specify the startup order for multiple operating system adapters in the system, up to four adapters can be selected as bootable adapters, and adapters can be added or removed.

Global properties: can set display and video modes, as well as whether to pause when displaying alert messages, including multiple configurable options.

Adapter properties: Allow viewing and modifying adapter settings, as well as accessing adapter device settings, including multiple configurable fields.

Device Properties: Provides viewing and updating functionality for various device settings of the adapter, including multiple configurable fields.

Exit SCSI BIOS Configuration Utility: As some changes only take effect after system restart, it is necessary to correctly exit the utility, press the Esc key, and respond to subsequent verification prompts, otherwise some changes may not take effect.

Basic Product Information

Product type: 32-bit optically isolated digital output board, specially designed and optimized for VMEbus, adopting dual Eurocard specifications, with 32 optically isolated high-level outputs.

Main functions: Implement digital output through VMEbus compatible logic, data control logic, and four 8-bit output registers, supporting 8-bit and 16 bit data transmission. The optocoupler isolates 32 outputs from each other and from VMEbus, supporting monitoring and non privileged data transmission.

Main characteristics

Equipped with 32 optically isolated outputs, the output current can be selected from 2.5mA or 300mA.

External pull-up voltage is provided to achieve maximum isolation, with on-site configurable pull-up resistors.

Capable of source or drain output, with a high output voltage tolerance of 30V in normal mode under low current options.

High isolation potential, capable of withstanding 1kV continuous voltage and 6kV pulse voltage, supporting positive or negative true options.

Supports 8-bit or 16 bit data transmission, with onboard DIP switches providing 14 bit board address selection. It adopts dual Eurocard format with front panel, allowing for on-site selection of non privileged or monitored short I/O transmission.

Application scenarios

Used for digital control of VMEbus, eliminating system grounding loops, controlling in high electrical noise environments, and controlling multi potential system components.

Ordering Options

Data polarity (A): 1 is positive true, 2 is negative true.

Output current (B): 0 is 2.5mA, 1 is 300mA.

CDE: All are 0 (reserved options for future use).

Special Sales Order (F): 0 is the standard VME front panel (without conforming coating), 1 is reserved, and 2 is the standard VME front panel (with conforming coating).

Connector data: Provides Panduit numbers for compatible cable connectors, strain eliminators, and PC board header connectors, also known as ITW/Pancon.

Functional characteristics

Compatibility: It is a standard dual height VME printed circuit board that is electrically and mechanically compatible with VMEbus.

Addressing scheme: It can be addressed to four 8-bit ports or two 16 bit registers, located on any 32-bit boundary within the short monitoring or short non privileged I/O space.

Board address: Selected by 14 onboard DIP switches, supports running in any available slot on the VMEbus backplane (except for slot 1).

VMEbus access: Address modification bits are decoded to support short monitoring or non privileged short I/O access, providing a single jumper to support this option, factory configured for short monitoring I/O access.

Data transmission types: D16, D8 (EO).

Access time: Maximum 250ns.

Output characteristics

Output current mode: There are high current and low current options, with specific parameters shown in Table 1.

Output configuration: including current absorption with pull-down resistor, current absorption without pull-down resistor, and voltage source (low current mode).

Output leakage current: The high current version has a maximum of 500 μ A under specific conditions; The low current version has a maximum of 50nA under specific conditions.

Output voltage: maximum 30V.

Switching time: see Table 1.

Output isolation: minimum 10M Ω.

Isolation voltage: The maximum continuous voltage from the site to VMEbus is 1000V, and 6000V lasts for 1 second; The maximum continuous voltage from channel to channel is 500V.

Physical/Environmental Specifications

Size: Dual height Eurocard, height 9.2 inches (233.4mm), depth 6.3 inches (160mm), thickness 0.8 inches (20.3mm).

Power requirement: Typical 1.5A at+5VDC, maximum 2.2A.

Airflow: Forced air convection, 400CFM.

Temperature: Operating temperature from 0 to+55 ° C, storage temperature from -20 to+85 ° C.

Altitude: Working altitude 0-10000 feet (3000m).

Humidity: Operating relative humidity of 20% to 80%, no condensation.

MTBF：153, 100 hours (under stress).

Output connector: Front panel 64 pin DIN connector.

Related products and applications

GE Fanuc embedded systems provide a wide range of digital I/O products for VME systems and support these products through comprehensive application information.

Specify factory options

To meet various control output requirements encountered in VMEbus applications, the following features of VMIVME-2170A can be specified as factory options: data polarity (positive or negative true), pull-up resistor socket (users can choose and install pull-up resistors), and output current (2.5 or 300mA absorption).

Product Overview

Basic information: VMIPCI-5565 is a PCI based reflective memory real-time fiber optic network product for GE Fanuc embedded systems, belonging to the VMIxxx-5565 series. It can be integrated into the network with other members of the series through standard fiber optic cables, and each board is called a node, allowing computers and other devices with different architectures and operating systems to share data in real time.

Key Features

A high-speed and easy-to-use fiber optic network with a serial rate of 2.12 Gbaud.

Supports PCI 64 bit 66MHz transmission, network operation does not require the involvement of a host processor.

Equipped with redundant operation mode, supporting up to 256 nodes.

The multi-mode fiber optic connection distance can reach up to 300 meters, and the packet size is dynamically variable (4-64 bytes).

The transmission rate varies depending on the packet size, with 47.1MB/s for 4-byte packets and 174MB/s for 64 byte packets.

Equipped with 64MB or 128MB SDRAM reflective memory with parity check, as well as two independent direct memory (DMA) channels, configurable byte order conversion to accommodate multiple CPU architectures on the same network.

Operating principle

Basic operation: Each node in the network is interconnected in a daisy chain loop through fiber optic cables, and each node needs to have a unique node ID (set through 8 onboard jumpers). The data transmission is initiated by the PCI host system writing data to the onboard SDRAM. During the writing process, the onboard circuit automatically writes the data and related information into the transmit FIFO, forming variable length data packets that are transmitted through the fiber optic interface. The receiver opens the data packet and stores it in the receive FIFO, then writes it into the local SDRAM and routes it to its own transmit FIFO until the data returns to the source node and is removed.

Register group: including PCI configuration registers, local configuration registers, runtime registers, DMA control registers, reflective memory (RFM) control and status registers. The functions and purposes of each register group are different, and some registers have different initialization methods and modification frequencies.

Reflective memory RAM: There are two specifications, 64MB or 128MB, with parity check. The starting position is specified by the base address register 3. The parity check function needs to be enabled by setting a specific register, and write operations need to be performed at the 32-bit or 64 bit boundary.

Interrupt circuit: There is a single PCI interrupt output (INTA #), and the interrupt source can be enabled and monitored separately through multiple registers. The interrupt circuit is divided into two layers, and the second layer interrupt is transmitted to the first layer through the LINTi # signal.

Redundant transmission mode: Removing the jumper blades between pins 1-2 of jumper E7 can configure it as redundant mode. At this time, each data packet is transmitted twice, and the receiving circuit evaluates the transmission situation. Although this mode reduces the probability of data loss, it will also lower the effective network transmission rate.

**Rogue packet removal operation * *: Rogue packets are packets that do not belong to any node in the network. VMIPCI-5565 can run as one of the two Rogue hosts to detect and remove rogue packets. After detection, relevant flags will be set and PCI interrupts can be triggered.

Configuration and Installation

Unpacking procedure: Components are sensitive to static electricity and should be handled on conductive materials. When not in use, they should be stored in their original packaging. Upon receipt, they should be inspected for any transportation damage and claims should be promptly processed.

Jumper configuration and position

The node ID is set by the 8 jumper blades of jumper block E4, and each node ID needs to be unique. Install the jumper blade so that the corresponding bit is low (0), and remove it so that it is high (1).

Jumper E7 controls three functions: 1-2 pins select non redundant or redundant network transmission mode, 3-4 pins enable or disable rogue host 0 function, 5-6 pins enable or disable rogue host 1 function, 7-8 pins are reserved pins and should not be installed with jumper blades. The default configuration is to install jumper blades on all pins except 7-8.

Physical installation: Before installation, it is necessary to ensure that the node ID and operation mode have been set. Power off the installation, firmly insert the board into the PCI connector and fix the screws, then reinstall the chassis cover and turn on the power. The board design complies with the PCI 2.2 specification.

Front panel description: There are three LED indicator lights, the red status LED is user-defined, and it is on by default when turned on. The status can be switched by writing to bit 31 of the control and status registers; The yellow signal detection LED lights up when the receiver detects light; The green self data LED lights up when it detects the return of its own data. There are also “RX” receiver ports and “TX” transmitter ports, which use “LC” type fiber optic cables. Dust caps should be installed when not connected to the cables, and eye injuries should be avoided when not powered.

Cable configuration: Provides cable specifications and connector specifications for multimode or single-mode fiber optic interfaces, including core diameter, cladding diameter, sheath outer diameter, attenuation, bandwidth, and other parameters, as well as connector compatibility, insertion loss, and other information.

Connectivity: Nodes are connected in a circular manner, as in the example of a circular connection of six nodes.

Programming

PCI configuration register: located in the 256 bytes of the PCI configuration space, the first 64 bytes are predefined headers that contain information such as vendor ID and device ID. Some registers can be modified by the user, while others are read-only or initialized by the system BIOS.

Local configuration registers: can be accessed through base address register offset 0 or 1, initialized to normal working configuration by serial EEPROM, and some registers can be modified by users to match the host system.

Runtime register: It is also accessed through the base address register offset 0 or 1, and will not be initialized by the serial EEPROM, maintaining the default state when the PCI bus is reset. Users need to modify some bits to activate the desired operating mode.

DMA control register: accessed through offset 0 or 1 of the base address register, it defaults to the PCI reset state and needs to be modified by the user to activate the operating mode, including DMA channel mode register, address register, etc., used to operate two DMA engines.

RFM control and status register: located in PLX local address space 0, the base address is specified by “PCI base address 2” in the PCI configuration register, including board revision register, node ID register, etc., to achieve the unique function of reflecting the memory board.

DMA operation example: It is necessary to find the value of the base address register 0, set five DMA registers, and then start the transfer and monitor the completion status by writing to the command/status register.

Example of network interrupt handling: including setting steps (clearing previous interrupts in FIFO, setting relevant registers to enable interrupts, etc.) and steps for serving network interrupts (reading registers to determine interrupt source, processing data and sender ID, etc.).

Maintain and comply with information

Maintenance: When the product malfunctions, it is necessary to first check the software, system configuration, electrical connections, etc. If a return is required, please contact GE Fanuc Embedded Systems to obtain a Return Merchandise Authorization (RMA) number. User level repairs are not recommended, and the drawings and charts in the manual are for reference only.

Compliance information: Complies with multiple international standards and regulations, such as the EU’s EN series standards, the US FCC Part 15, and Australia/New Zealand’s AS/NZS CISPR 22. Compliance requirements and restrictions vary in different regions.

Basic Information

Product Name: VMIAC-5595 2 Gb/s Reflective Memory Hub Component

Production company: GE Fanuc Automation (Embedded Systems Division)

Document information: Published on May 16, 2007, document number 800-805595-000 E. Specifications may change without prior notice

Main features

VMIxxx-5565 Reflective Memory Network Product for GE Fanuc Embedded Systems

Use small form factor pluggable (SFP) transceivers, providing up to 8 ports

Hub components can be cascaded and support up to 256 nodes

Automatically bypass defective or disconnected nodes in fiber optic networks

The automatic bypass function can be controlled by signal loss or synchronization mode loss

Regenerate serial optical signals at each port, eliminate link loss and reduce jitter

Can be configured to use cables up to 10km in length

10BaseT Ethernet TCP/IP port for remote access and control

RS232 port is used for local access and control

Optional 19 inch 1U rack installation or desktop enclosure

Built in universal power supply

Dark to Dark “option: If the receiver does not detect a signal, the onboard transmitter can be turned off (applicable to firmware version 02.00 and higher)

Ordering Options

Option Description

A (shell option) 0=reserved; 1=Reserved; 2=Rack installation or desktop

B (number of single mode (10km) pluggable transceivers) 0, 1, 2, 3, 4, 5, 6, 7 or 8

C (number of multi-mode pluggable transceivers) 0, 1, 2, 3, 4, 5, 6, 7, or 8

Cable specifications

1. Simplex cable specifications

Fiber optic cable – multimode 62.5 micron core

Fiber optic cable assembly: VMICBL-000-F5, cable length code ABC corresponds to different lengths, such as 000=0.5 feet (0.15m), 001=1 foot (0.31m), etc

2. Duplex cable specifications

Fiber optic cable – multimode; 62.5 micron core

Fiber optic cable assembly: VMICBL-000-F6, cable length code ABC corresponds to different lengths, such as 000=3 feet (1m), 001=6 feet (2m), etc

Functional characteristics

1. Port wavelength and distance

Multimode port wavelength: 830 to 860nm, multimode cable length: maximum 300m

Single mode (10km) port wavelength: 1300 to 1335nm, single mode (10km) cable length: maximum 10km

Single mode (80km) port wavelength: 1540 to 1570nm, single mode (10km) cable length: maximum 80km

2. Core functions

It is a hosted hub designed to be used in conjunction with GE Fanuc’s VMIxxx-5565 series reflective memory real-time network products for embedded systems

When signal loss or loss of effective synchronization mode is detected, the port can be automatically bypassed to keep other nodes in the network running

The optical port adopts a small form factor pluggable (SFP) transceiver, which only needs to be configured with the required port. It can be combined with multi-mode (short distance) or single-mode (long distance) transceivers to save small network costs and optimize the system

For large networks, multiple VMIAC-5595 components can be cascaded, supporting up to 256 nodes

The reflective memory network can be monitored and controlled through a simple PC serial port (RS232 port) or through a local area network (LAN) or web browser (Ethernet port)

3. Control and Status

Additional control registers allow manual disabling of transmitters on any port

The front panel manual switch includes a received momentary reset switch and a Gang Select switch. The Gang Select switch configures the VMIACC-5595 port as an 8-port loop or two independent 4-port loops

The three LEDs next to each port provide visual indications of port status, and additional status indications and operating modes can be obtained through serial or Ethernet ports

The status information includes detection of installed transceivers, detection of signals (light), detection of effective synchronization modes, and port operation speed (2Gb/s)

Control registers allow channel bypassing based on the absence of a single valid synchronization mode or multiple synchronization modes, as well as signal (light) loss. Each port can be manually activated or bypassed, regardless of the status indicator

4. Ethernet controller

10BaseT interface conforms to Transmission Control Protocol/Internet Protocol (TCP/IP) standard

Each hub component has a unique MAC address and can run on a local area network (LAN) or a wide area network (WAN)

Contains a remote user interface available via standard Ethernet connection, controlled by a standard HTML based web browser, displaying status data, supporting bypass mode, “dark to dark”, and forcing each port on/off or automatic, all of which are saved in NVRAM

Physical/Environmental Specifications

1. Size

Desktop component size: 16.73 inches wide x 10.0 inches deep x (1U) 1.72 inches high (excluding non slip self-adhesive feet)

Rack mounting component size: Same as the basic size of desktop components, but includes two 1U rack mounting brackets for standard 19 inch racks

2. Connectors

Front panel connectors: 8 industry standard SFP transceivers, SFP sockets without transceivers include EMI dust plugs, 1 RJ45 Ethernet connector, and 1 9-pin female D-subminiature RS232 connector

Rear panel connector: includes power input module, including power on/off switch, 4A/250V fuse, and globally compatible IEC socket

3. Wiring

Each installed SFP transceiver requires one duplex LC fiber optic cable or two simplex LC fiber optic cables. Simplex cables are best suited for cascading hubs, while duplex cables can be used for all other interconnections

4. Power requirements

90 to 264VAC, 47 to 440Hz, 25W

The power supply and power input module comply with safety standards: UL, C-UL: UL 1950; TUV：EN69050； CE：EN55022、EN61000-4-2、3、4、5； EN61000-3-2

Fuse: 1A, 250V, 5 × 20mm, fast acting, IEC 60127-2 standard glass or equivalent product

5. Environmental parameters

Temperature: Operating temperature from 0 ° C to+65 ° C; Storage temperature from -40 ° C to+85 ° C

Humidity: Operating relative humidity of 20% to 80%, no condensation; Storage relative humidity of 20% to 80%, no condensation

MTBF: total fit x quantity: 2317.3641; MTBF (hour): 431524.76

6. Regulatory certification

EU (CE mark): Complies with multiple standards such as EN55024, EN55022 Radiation Emission Class A, etc

United States: FCC Part 15, Class A

Canada: ICES-003, Grade A

Safety: Designed to comply with safety standards such as UL60950 and EN60950 (LVD)

Basic Information

Product Name: VME-3125A Isolation Scan 12 Bit 32 Channel Analog to Digital Converter Board (with Built in Testing Function)

Production company: Abaco Systems

Main features

32 single ended or 16 differential inputs

Automatic scanning, continuously digitizing input and storing results in dual port data registers

Input range: Bipolar ± 50mV to ± 10V, Monopolar 0-100mV to 0-10V, or 0 to 25mA current input options

Jumper programmable gains x1, x10, x100

1 12 bit A/D converter with built-in tracking and holding functions

Start scanning without software startup

Pause and lock scanning function, which can achieve 40KSPS arbitrary channel sampling based on channel pointer

Optional A/D range: ± 5V, ± 10V, 0 to+10V

40kHz total conversion rate

Support real-time built-in testing (BIT)

Input connector compatible with discrete and ribbon cables

Optional data encoding: offset binary or binary complement

Over voltage protect

Low pass input filter: 50kHz, optional 40Hz

Pull down resistor to prevent input floating

1000V analog ground/digital ground isolator

Ordering Options

Option Description

A (input option) 0=50kHz input filter (-3dB cut-off frequency, voltage input); 1=40Hz input filter (-3dB cut-off frequency, voltage input); 2=250 Ω 0.01% terminal (high-precision current input); 3=500 Ω 0.01% terminal (high-precision current input)

BCD 0 (reserved for future options)

E (Special Sales Order) 0=Standard; 1=Reserved for CCS

F (conforming coating) 0=standard VME front panel without conforming coating; 1=Reserved; 2=Standard VME front panel with conforming coating; 3=Reserved

Compatible cable connectors

Standard 37 pin ultra small D-type male connector

Discrete cabling: AMP 747916-2 (with 206478-4 enclosure)

Ribbon cable: AMP 747306-1

Functional characteristics

1. Basic Introduction

VME-3125A provides isolated 12 bit analog-to-digital conversion with 32 single ended analog voltage input channels (16 differential) for VMEbus’s 6U Eurocard. The optional gain and A/D range support an input voltage range of ± 50mV to ± 10V, and the current input option supports 32 single ended channels with ranges of 0 to 20mA, 4 to 20mA, and 5 to 25mA. To minimize system software overhead, all inputs are continuously scanned and digitized at a total sampling rate of 40000 samples per second, and the measurement data of each channel is accessed by VMEbus at any time through a dual port data register. For voltage input, a 40Hz low-pass input filter can be selected to minimize the impact of system noise, and the standard unit is equipped with a 50kHz low-pass filter.

2. Core functions

Programmable Gain Amplifier (PGA): Jumper options include series voltage gain x1, x10, or x100 for all channels; For voltage input, the full range of the A/D converter can be selected as ± 5V, ± 10V, or 0 to+10V; the data encoding software can be selected as offset binary or binary complement code

Input configuration: The input can be configured with 16 differential voltage channels or 32 single ended voltage or current channels through jumper wires; A single front panel 37 pin ultra small D-type connector provides connections for all input channels

Working mode: All 16 or 32 input channels are continuously scanned at the maximum sampling rate, and the resulting data is stored in a dual port data register for VMEbus to access; After any reset operation, the scan automatically starts without the need for additional programming to initiate the A/D conversion process

Built in Test Function (BIT): By selecting the BIT working mode, the operation of PGA, ADC, and related control logic can be verified. In this mode, the internal reference voltage is applied to the input of PGA, bypassing the analog input multiplexer. All data channels read through the control interface will reflect the selected BIT reference voltage

3. Features related to VMEbus

Compliance: Compliant with VMEbus standard ANSI/IEEE STD 1014-1987, IEC 821 and 297, with 6U external dimensions

Board address: The physical address is selected through the onboard address jumper, using VMEbus address lines A07 to A15; The VME-3125A board occupies 128 bytes of address space and can be located on any 64 word boundary of the short I/O (A16) space

Address Modifier: Address modifier bits are selected and decoded through jumpers to respond to non privileged short I/O access, monitoring short I/O access, or both access privileges

4. System reset and indicator lights

System reset: System reset establishes the following board states: all channels automatically scan, front panel diagnostic LED indicator lights up, offset binary data format

Front panel system diagnostic LED: The software controlled front panel LED lights up when the system is reset and can be turned off under software control to provide an external indication that the built-in test has been completed

Simulate input data format

The analog input is digitized and stored in 32 dual port data registers (16 registers for differential operation) as a 12 bit right aligned digital value. The software can select data codes as offset binary and binary complement. In binary complement encoding, the sign bit (D11) is extended to the most significant bit (D12 to D15) of the data register.

Input characteristics

(At+25 ° C and rated power supply, unless otherwise specified)

Number of channels: 32 single ended or 16 differential voltage input channels; 32 single ended current input channels

Voltage range: ± 50mV to ± 10V (bipolar) or 0 to+100mV, 0 to+10V (unipolar), factory configured for ± 10V input range

Current terminal: Suitable for single ended, 0-10V, and X1 gain unipolar configurations, with two options: 250 Ω 0.01% and 500 Ω 0.01%

Current range: According to the applicable input range of the terminal, 250 Ω corresponds to 0 to 20mA, 4 to 20mA, 5 to 25mA; 500 Ω corresponds to 0 to 20mA, 4 to 20mA

Input impedance: When the power is turned on, the voltage input options are DC differential 27M Ω, DC common mode 1.3M Ω, AC differential 9K Ω, and AC common mode 9K Ω. When the power is turned off, the DC differential 11K Ω, DC common mode 6K Ω, AC differential 9K Ω, and AC common mode 5K Ω

Input bias current: minimum 44nA/maximum 90nA

Input bias current drift: 0.30nA/° C

Common mode voltage (CMV): When the differential input is at zero input signal, the maximum ± 11V; CMV refers to the common analog ground of all inputs; For other gains, the formula is ± 11V=(VCM+Vddiff/2) * gain

Common mode rejection ratio (CMRR): Differential input has different minimum/typical values (dB) at different gains and ADC ranges when the source is unbalanced at 350 Ω and the frequency is between DC and 60Hz

Input to VMEbus isolation: 1000VDC

Input noise: Under 10 to 1000Hz and 3 σ, different gains and ranges have different maximum noise (mV p-p) in single ended mode

Each input bandwidth: DC to Fc, where Fc is 50kHz for a 50kHz filter and 40Hz for a 40Hz filter option unit

Input filter: Single pole passive low-pass filter, -3dB at 50kHz or 40Hz ± 20% (voltage input option only)

Overvoltage protection: maximum ± 40V continuous during power supply; ± 25V during power outage

Transmission characteristics

(At+25 ° C and rated power supply, unless otherwise specified)

Measurement resolution: 12 bits

Channel scanning rate: minimum 40KSPS (thousand samples/second) total rate

Voltage transfer function:

E IN=E LO+E FSR × 4096N ADC, where E IN=input voltage, E LO=lower end of input range,

E FSR=full-scale input range, N ADC=A/D converter reading

Current transfer function: I IN=R TERMINATION E FSR × N ADC/4096, where I IN=input current (ampere), E FSR=10V (unipolar), N ADC=A/D converter reading, R TERMINATION=250 Ω or 500 Ω options

Input range of A/D converter: ± 5V, ± 10V, 0 to+10V, jumper optional

Input gain of A/D converter: x1, x10, x100 (± 0.3%, jumper optional)

Accuracy: Voltage input=± 0.04% reading ± 0.03% range ± 2.0mV; Current input (-200, -300 options)=± 0.05% range ± 2.44 μ A

Temperature stability: The voltage input board option (mV/° C) is ± 30PPM reading ± 25PPM range ± 20 μ V; The current input board option (μ A/° C) is ± 40PPM reading ± 25PPM range ± 20nA

Long term drift: ± 50PPM reading ± 45PPM range ± 100 μ V every 1000 hours

Channel crosstalk: In ± 10V bipolar and gain X1 differential mode, different options have different typical/maximum values (dB) for DC and AC inputs

BIT reference voltage: Software options include 0.000V,+4.980V,+0.4928V, and 9.91mV

BIT reference accuracy: ± 30mV ± 30PPM/° C (4.98VDC)

Physical/Environmental Specifications

Size: Standard VME double height board 160 × 233.5mm

Power requirement:+5VDC (± 5%), maximum 1.5A

Temperature: Operating temperature from 0 ° C to+65 ° C; Storage temperature from -40 ° C to+85 ° C

Humidity: Operating relative humidity of 20% to 80%, no condensation

Cooling: forced air convection (standard VME slot)

MTBF: Contact the factory

Input connector (P3): 37 pin ultra small D-type female connector

Basic Information

Product Name: VME-3122A High Performance 16 Bit Analog to Digital Converter (ADC) Board

Production company: GE Fanuc Intelligent Platforms

Main features

64 different or single ended inputs

16 bit analog-to-digital (A/D) conversion

Software selectable conversion rate (maximum 100kHz)

Programmable options for scanning channels 1, 8, 16, 32, or 64

Continuously digitize the selected input channel and store the results

Three triggering modes: software triggering, external triggering, and interval timer triggering

Three scanning modes: automatic scanning, single scan, and random access

Programmable VME interrupt

User programmable interval timer

Software programmable gains 1 and 10

External triggering can synchronize multiple boards simultaneously

Jumper selectable A/D range: 0 to+5V, 0 to+10V, ± 2.5V, ± 5V, and ± 10V

Optional low-pass filter

Over voltage protect

1024 word data buffer (16 word deep buffer x 64 channels)

Optional output encoding

When powered on, it is in automatic scanning mode with a gain of 1

Application Fields

Factory automation and instrumentation

process control

laboratory instruments

Machine monitoring

data acquisition

Ordering Options

Option Description

A (input filter option) 0=no filter; 1=10Hz（-3dB）； 2=50Hz（-3dB）； 3=100Hz（-3dB）； 4=500Hz（-3dB）

B (channel quantity option) 0=64 channels high performance; 1=32 channels high performance; 2=16 channels high performance

C (input option) 0=differential analog input channel with 96 pin non latch connector; 1=Single ended analog input channel with 96 pin non latch connector; 2=Differential analog input channel with 64 pin latch connector; 3=Single ended analog input channel with 64 pin latch connector

DE 0 (reserved for future options)

F (Special Sales Order) 0=Standard VME front panel without conforming coating; 1=Reserved; 2=Standard VME front panel with conforming coating

Connector data

Recommended style for connecting components P3 and P4 I/O connectors

64 pin IDC mating connector (64 pin) Panduit 120-964-435

Strain relief (applicable to 64 pin connectors) Panduit 100-000-072

96 pin discrete mating connector (96 pin discrete) AMP 925486-1

Female crimping contact (96 pin discrete) AMP 530151-6

Connector housing (suitable for 96 pin connectors) Harting 09 03 096 0501

96 pin IDC mating connector (96 pin large-scale termination) ERNI 913.031

0.033-inch ribbon cable (96 pin large-scale termination) ERNI 913.049

Strain relief insert (0.033-inch ribbon cable) Harting 09 02 000 9912

Connector housing (suitable for 96 pin connectors) Harting 09 03 096 0501

PC board I/O connector part number Panduit 101-096-033A

Functional characteristics

1. Working mode

MODE

Software trigger: Start the selected scanning mode by writing the software trigger address

External trigger: The external trigger received on the P2 connector initiates the selected scanning mode

Interval timer trigger: Start the selected scanning mode each time the programmed time interval expires

SCAN

Automatic scanning: default scanning mode, all active channels are scanned continuously in order

Single scan: Start a single data burst (scanning all selected channels) from the selected trigger mode, stop and wait for another trigger after scanning all selected channels

Random access: Each time the selected trigger mode is enabled, a single channel can be selected, digitized, and stored

Channel automatic gain: The unique gain code for each channel is loaded from VME into the gain buffer, and the allocated code is retrieved in real-time from the buffer during each channel acquisition

Synchronization: A single scan or burst can be initiated by an external TTL trigger through the P2 connector (external trigger) or a local trigger through the control and status register (CSR) (software trigger), and any event will generate a P2 trigger output, which can be used to synchronize up to 15 cards

2. VME related characteristics

VME access: The response to the address modifier can be selected as A32, A24, or A16 address space through jumper wires; Monitoring or user privileges, or both

VMEbus compliance: Compliant with VMEbus specifications ANSI/IEEE STD 1014-1987, IEC 821 and 297, with 6U external dimensions

VME interrupt: An interrupt request can be generated at the end or in the middle of a buffer scan, or it can be initiated after collecting a specific number of samples (1 to 65535), and the response vector is controlled through the interrupt vector register

Data ready flag: When the data buffer is full (end of scan) or half full (middle of scan), the data ready flag in CSR is set

Interval timer: Programmable interval timer provides a time interval of up to 687 seconds

3. Reset operation

Board reset response system reset or writing software reset address

The reset operation automatically establishes the following default conditions: automatic scanning mode, 64 channel block size, 64 channel data buffer, channel gain=x1, 100kHz conversion rate

ADC will undergo a calibration cycle under any reset condition, which takes 41ms after the reset operation is initiated

4. Other functions

PGA: Channel gains of x1 and x10 can be selected through a programmable gain amplifier (PGA). The PGA gain can be configured through software as a single gain for all channels, or real-time control can be used to assign unique gains to each channel

Panel indicator: The front panel LED controlled by the program is powered on during the reset period and turned off through CSR

Board Identification: The Board Identification Register (BIR) contains the VME-3122A identification code

Input characteristics

Number of input channels: 64, 32, or 16 differential or single ended channels

Full range A/D range: ± 2.5V, ± 5V, ± 10V, 0 to+5V, 0 to+10V, jumper optional

Channel gain: Software configuration is x1 or x10

Full range input range

Gain=1: ± 2.5V to ± 10V (bipolar); 0 to+5V, 0 to+10V (unipolar)

Gain=10: ± 250mV to ± 1V (bipolar); 0 to+0.5V, 0 to 1V (unipolar)

Accuracy (% of FSR): There are different values for different ranges and gains, based on the average of 1000 samples

Stability: Temperature drift, per degree Celsius=± 25PPM (ADC reading) plus ± 5PPM (ADC range) plus ± 2.5 µ V

Input noise: (0.4+0.3/G) mV, where G=PGA gain (noise is independent of filter options)

Input bias current (typical/maximum): 50/120nA

Input impedance (minimum): Different DC differential, DC common mode, AC differential, and AC common mode impedances when the power is turned on and off

Channel crosstalk (DC to 1kHz): 80dB between adjacent channels within ± 10V range; 70dB between adjacent channels within ± 2.5V range

Common mode voltage range: (IVCM |+| VIN |. G) ≤ 10V, where VCM=common mode voltage, VIN=input voltage, G=gain

Common mode rejection: From DC to 60Hz, when the 350 Ω source is unbalanced, the minimum common mode rejection for gain 1 is 68dB, typical 80dB; the minimum common mode rejection for gain 10 is 76dB, typical 89dB; the minimum common mode rejection for+5V and ± 2.5V ranges is 66dB, which can be adjusted on-site to achieve the same common mode rejection as gain 1

Overvoltage protection: ± 35V (continuous) power on/off; ± 80V (transient, maximum 1s)

Input filter: Optional low-pass single pole filter with different -3dB values at different frequencies, frequency doubling in single ended (pseudo differential) applications, cut-off frequency tolerance of ± 25%, unfiltered input bandwidth (20Vp-p) typically 40kHz

Common mode/floating input protection: Both sides of each input are grounded through a 22M Ω resistor

Transmission characteristics

Resolution: 16 bits

Input sampling: order, starting from channel 00

Input transfer function:

E IN=E LO+E FSR × 65536N ADC, where E IN=input voltage, E LO=lower end of input range, E FSR=full-scale input range, N ADC=A/D converter reading

A/D conversion rate: 381 to 100kSPS

Channel sampling rate (maximum): 100kSPS (100kSPS ÷ number of channels in the scan block, minimum 1 channel)

Time interval: 305 µ s to 687s

Data encoding: programmable to choose binary complement or direct/offset binary

Data buffer storage

Buffer size: 16 to 1024 consecutive 16 bit data words, program controlled

Block size: 1, 8, 16, 32 or 64 channels, program controlled

Access time: maximum 600ns during non scanning; typical 600ns during scanning, maximum 1.2 µ s (maximum access time in scanning mode only occurs when VME access occurs within the ADC sampling window)

VME access: D8 to or D16

Availability: Can be accessed from VME at any time, buffer and block sizes are controlled through configuration control registers (CCR)

Physical/Environmental Specifications

Size: 6U (4HP) single slot Eurocard shape

Height: 9.2 inches (233.4mm)

Depth: 6.3 inches (160mm)

Thickness: 0.8 inches (20.3mm)

Power requirement: 3.0A at+5VDC (maximum)

Airflow: Forced air cooling is required

Temperature: Operating temperature 0 to+65 ° C; Storage temperature -40 to+85 ° C

Altitude: Working at 0-10000 feet (3000m); Storage 0-40000 feet (12000m)

Humidity: Working relative humidity 0% to 80%, no condensation

Input connectors (P3, P4): can be ordered as 96 pin DIN non latch or 64 pin DIN latch. The center row of the 96 pin non latch connector is grounded, while the center row of the 64 pin latch connector is not grounded. When using the 64 pin latch connector in differential mode, users can provide grounding on the front panel jumpers E1 and E2, which will result in channels 31 and 63 being configured as single ended

UIOC support

In UIOC, VME-3122A is used as a monitoring device. During initialization, UIOC programs VME-3122A to scan all 64 channels and sets the scanning mode to automatic scanning. Through UCLIO ™ Language, users can set programmable channel gains and command UIOC to retrieve data from any or all channels of VME-3122A. Through a menu driven calibration process, users can create and store channel gain and offset correction factors, which UIOC automatically uses to provide software gain and offset correction for each channel.